1. Field of the Invention
This invention relates to a novel DRAM cache structure, the associated circuits and method of operations suitable for high-speed caches, such as write-through caches.
2. Description of Background
Before our invention conventional caches (such as level ‘1’, ‘2’) embedded in high-speed processors are made up of static random access memory (SRAM) for high speed and refresh-free operations. Refresh-free is important as refresh operations required for dynamic random access memory (DRAM) reduces read availability and hence reduces system performance. This is especially crucial for level ‘1’ (L1) and level ‘2’ (L2) caches since they are closest to the execution unit and must have a relatively short latency, so adding a refresh cycle could contribute a relatively large performance penalty. With the recent advent of DRAM cells with gated diode (such as the 2T1D, 3T1D) DRAM speeds are now comparable to that of conventional SRAM. Further, they are better in low voltage scaling, and are more tolerant to various process variations, addressing the voltage scaling issue and variability issues facing SRAM for future generations of technologies. The remaining major hurdle for these DRAM's is the ability to reduce or hide refresh cycles, so as to minimize read and write stalls. Usually, with proper scheduling of write operations and buffering of write data, stalls can be minimized. For read operations in low latency DRAM caches, the refresh cycles would potentially lead to read stalls and higher miss rates (lower performance). Further, a significant amount of power is required to refresh the DRAM cells. The refresh circuits needed for a DRAM cache add complexity, have architecture and performance impacts, and require architectural changes for replacing SRAM with DRAM in the caches of conventional processors.
There is a long felt need for a novel DRAM cache structure for high speed, low-level caches that does not require refresh operations. Such a structure must also incorporate mechanisms for the detection of multi-bit errors resulting from the alteration of stored charges in the DRAM cells due either to leakage (retention error) or to radiation events (soft error). This in part gives rise to the present invention.